The present invention generally relates to the design of integrated circuit devices and, more particularly, to monitoring digital event performance using an analog circuit.
It is desirable to monitor the performance of digital circuits for a variety of purposes. As component and circuit physical size decrease, and the complexity and speed of integrated circuits increases, entire systems comprising a plurality of functional blocks are contained in single chips. In order to monitor the performance of these systems, or portions thereof, large numbers of monitors are deployed in different locations on the chip to get a good performance evaluation of the system. One method to monitor the performance of digital circuits is to count the quantity of digital operations occurring within a known period of time.
Counting digital events as a way of measuring performance has conventionally been accomplished using binary counter circuits. An advantage of using binary counters is the ability to count digital events precisely. A typical binary counter capacity is in the range of 10 to 20 bits in length, the capacity being designed to accommodate the quantity of expected events. Binary counter capacity is limited by the amount of physical space necessary to construct each counter, the space available, the circuit complexity needed to interconnect the counter, and the operation time required to periodically interrogate the counter""s stored information.
Despite providing a precise event count, several significant disadvantages are also associated with digital counters. As clock speeds continue to increase, the rate and quantity of digital events occurring within a fixed time period also increase. This increase in the quantity of digital events to count can quickly consume the capacity of a binary counter. Increasing binary counter capacity commensurate with increased clock speed requires more overhead circuitry, such as a long scan chain to improve the testability of the counter. The complexity of large binary counters, and the accompanying circuitry necessary to interconnect larger digital counters to other performance monitoring logic, also increases costs and occupies valuable integrated circuit space. In many digital event performance evaluation applications, a precise event count is not necessary. In some evaluation applications, an approximate count of the entire population is adequate, for example, in regulating system chip power or dispatching chip cooling mechanisms.
A method and circuit for monitoring the performance of digital systems that address the aforementioned problems, as well as other related problems, are therefore desirable.
The present invention is directed to an analog method and circuit arrangement for monitoring digital event performance. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, an analog performance monitoring method and circuit arrangement are provided. The circuit arrangement is adapted to approximately count a plurality of digital event pulses. The circuit arrangement includes a switching circuit coupled between a constant current source and a capacitor. In one example embodiment, the constant current source is a biased field effect transistor (xe2x80x9cFETxe2x80x9d) and power supply. Each digital event pulse controls the switching circuit to pass a substantially fixed amount of charge from the constant current source to accumulate in the capacitor. In one example embodiment, the switching circuit is a transistor responsive to the digital event pulses, the capacitor operating in a linear voltage range wherein capacitor voltage is approximately linear in proportion to the accumulated capacitor charge. In one example embodiment, the capacitor has a capacity to accumulate a substantially fixed amount of charge for each of at least 100,000 digital event pulses. A comparator circuit is coupled to the capacitor and a voltage divider circuit. The comparator circuit generates an output signal responsive to the quantity of digital events counted, as represented by charge accumulated in the capacitor, with respect to a voltage threshold level selected by the voltage divider circuit. In another example embodiment, the voltage divider is programmable and provides a controllable count threshold. A reset circuit discharges the capacitor to a known starting charge level, for example, to a substantially zero charge level.
According to another example embodiment of the present invention, the constant current source comprises a switching transistor and a power supply, the switching transistor being biased in a constant drain current operating region.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.